1. Field of the Invention
The present invention relates to a thin film transistor (“TFT”) formed on a flexible substrate and a method of manufacturing the same, and more particularly, to a TFT formed on a flexible substrate having uniform characteristics and a method of manufacturing the same.
2. Description of the Related Art
Cathode ray tube (“CRT”) displays are rapidly replaced by flat panel displays in the present display markets. Leading flat panel displays include liquid crystal displays (“LCDs”) and plasma display panels (“PDPs”). In flat panel displays, thin film transistors (“TFTs”) are usually used as switching devices.
As techniques that can form TFTs at a low temperature are introduced, the TFTs are formed on a flexible substrate such as transparent plastic or glass. As the flexible substrate is used, the flat panel displays can be modified to various forms and the application field thereof can be widened. However, problems occur in the process of forming the TFT on the flexible substrate. For example, according to the location in the flexible substrate where the TFT is formed, the characteristics of the TFT vary.
The variation of characteristics of a TFT according to the location will now be described through a process of forming the TFT on a flexible substrate.
FIG. 1 is a cross-sectional view illustrating a conventional TFT of the prior art formed on a mask aligning reference position of a flexible substrate.
Referring to FIG. 1, a poly silicon film 12 is formed on a flexible glass substrate 10. The poly silicon film 12 is divided into several regions. That is, the poly silicon film 12 includes separated first and second N+ or P+ dopant regions 14 and 16, a channel region 18, and first and second off-set regions, or lightly doped drain (“LDD”) regions, a1 and a2. The channel region 18 is located between the first and second N+ or P+ dopant regions 14 and 16, and is separated from the first and second N+ or P+ dopant regions 14 and 16 by the first and second off-set regions a1 and a2, respectively. The first and second off-set regions a1 and a2 are not doped with a conductive dopant. The first off-set region a1 is located between the first N+ or P+ dopant region 14 and the channel region 18, and the second off-set region a2 is located between the second N+ or P+ dopant region 16 and the channel region 18. A gate oxide film 20 is formed on the channel region 18 of the poly silicon film 12. A gate electrode 22 is formed on the gate oxide film 20. The gate oxide film 20 is a silicon dioxide SiO2 film, and the gate electrode 22 is a metal electrode formed of aluminum neodymium AlNd etc.
As described above, the conventional TFT formed on a mask aligning reference position of a flexible substrate includes the first and second off-set regions (or LDD) a1 and a2 which are symmetrical with respect to the channel region 18. Therefore, the conventional TFT that has off-set regions as depicted in FIG. 1 has a smaller leakage current than a conventional TFT that does not have the off-set regions. However, the conventional TFT has the following drawbacks. That is, in the TFT formed on a mask aligning reference position as depicted in FIG. 1, the first and second off-set regions (or LDD) a1 and a2 are symmetrical with respect to the channel region 18, but in the TFT formed on a location separated from the mask aligning reference position as depicted in FIG. 2, the first and second off-set regions (or LDD) a1 and a2 are asymmetrical with respect to the channel region 18 and one of the two off-set regions, in the illustrated case the first off-set region a1, is almost not present. This is because an aligning error of the TFT formed on a location separated from the mask aligning reference position exceeds an error tolerance in aligning a mask used for forming the gate electrode due to thermal expansion of the flexible glass substrate 10 during various processes prior to forming the gate electrode 22. As the TFT depicted in FIG. 2, if the first off-set region a1 is almost not present and the second off-set region a2 is relatively wide, the possibility of causing a leakage current between the first N+ or P+ dopant region 14 and the gate electrode 22 increases.
In the case of the conventional TFT formed on a flexible substrate as described above, there is almost no leakage current problem when the conventional TFT is formed on the mask aligning reference position, but the conventional TFT formed on a location separated from the mask aligning reference position is not free from the leakage current problem. Therefore, the conventional TFT formed on a flexible substrate can have different operation characteristics according to the forming location of the TFT even at the same operation condition.